Study Guide | EEE 105 Module 4

UP EEEi | Lawrence Quizon


Module Intro

In this module, you will learn how to implement a single-cycle processor. For starters, remember how a finite state machine works. A processor is essentially a large finite state machine, whose state variables are its register file and the data memory together called the “architectural state”. Its inputs are the instruction memory and the program counter. Whatever you put into the instruction memory is the input, and it influences how the state variables of the processor evolve.


Topic 1: Single Cycle Datapath Part 1 - R-type Instructions

We first start by learning how instructions are fetched from memory, and then we will study how we can build a datapath that supports R-type arithmetic instructions.

Watch the lecture below:

Study Questions

  1. What do we need to add or change in the datapath to support AND and OR instructions?
  2. To support the immediate addressing instructions ADDI and SUBI, what do we need to add to the datapath?


Topic 2: Single Cycle Datapath Part 2 - Complete Datapath: Loads and Branches

A processor that can only do ADD and SUB instructions isn’t very useful. We need to support the memory and branch instructions to create a more useful processor. To do this, we need to add a few more things to the datapath.

Watch the lecture below:


Study Questions

  1. If a MUX introduces 2ns of delay to the datapath and \(T_{SU}=1ns\), what is now the maximum allowable clock frequency for this single-cycle processor?
  2. If we were to merge the instruction memory and the data memory into one, what would we need to change? Can this processor still work in one cycle?

Quiz

In light of the upcoming reading break (Oct 24-28), there is no quiz for this module! Please await the problem set to be released during module 4.